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  1. Home
  2. Vocab
  3. Fabless

Fabless

A semiconductor company that designs chips but outsources all physical manufacturing to foundries.

Year: 2012Generality: 383
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A fabless company is a semiconductor business that focuses entirely on the design and marketing of chips while contracting out physical fabrication to specialized manufacturing partners called foundries. Rather than investing billions of dollars in cleanrooms, lithography equipment, and process engineering, fabless firms concentrate their resources on chip architecture, IP development, and system-level design. Foundry partners such as TSMC and Samsung handle the capital-intensive work of etching circuits onto silicon wafers at increasingly fine process nodes.

This division of labor became strategically important to machine learning hardware as the AI boom drove demand for highly specialized accelerators. Companies like NVIDIA, AMD, and a wave of AI-focused startups—Cerebras, Groq, SambaNova—operate as fabless designers, enabling them to iterate rapidly on GPU and tensor processing architectures without owning manufacturing infrastructure. The model lowers the barrier to entry for chip design, allowing ML-focused teams to bring novel architectures to market faster than vertically integrated competitors.

The fabless model carries meaningful implications for the AI supply chain. Because leading-edge fabrication is concentrated at a small number of foundries, fabless AI chip companies are exposed to geopolitical risk, capacity constraints, and process-node availability. The performance of any given ML accelerator depends not only on its architectural design but on the foundry's ability to deliver a particular node—such as TSMC's 3nm or 5nm processes—at scale. Understanding the fabless structure helps explain both the rapid architectural innovation seen in AI hardware and the supply bottlenecks that periodically constrain the availability of training and inference chips.

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Disaggregated Inference
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A model serving technique that separates LLM inference into specialized hardware for prompt processing (prefill) and token generation (decode), enabling higher throughput and lower power at the cost of deployment flexibility.

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